Panasonic MN103001G/F01K - Manual (Page 423)

I/O Ports
15-57
15.13 Port B
15.13.1 Block Diagram
Fig. 15-13-1 shows a block diagram for port B.
Fig. 15-13-1 Port B Block Diagram (PB7 to PB0)
Internal data bus
M
P
X PBn
(n=7,6,5,4,3,2,1,0)
PBOUT
A15 (n=7)
to A8 (n=0)
PBM
PBMD
PBDIR
PBnD
PBnO
P... Represents one bit of each register.
M
P
X
PBPU
PBnI
PBIN
A15 to A8
output enable
signal
ADM15 (n=7)
to ADM8 (n=0)
or