Panasonic MN103001G/F01K User Manual
Page 51
2-17
CPU
[Interrupt Accept Group Register (IAGR)]
R halfword/byte access
During a register read, the interrupt accept group register (IAGR) indicates the smallest group number of the groups
that are generating an interrupt of the interrupt levels accepted by the CPU, which are indicated by IM2 to IM0 of
the PSW. This register is allocated to address x'34000200 in the internal I/O space. The GN4 to GN0 field (5 bits)
corresponds to the interrupt group number. A branch destination of the interrupt program for each group can be
found, for example, by referencing the contents of the address obtained by adding the interrupt accept group register
value to the leading address of the interrupt vector table. The interrupt accept group register is a read only register,
and writing cannot be performed. When there are no interrupt factors of the applicable interrupt level, IAGR
becomes 0.
Accessing IAGR is meaningless during non-maskable interrupts.
Fig. 2-5-3 Interrupt Accept Group Register
[Interrupt Vector Address Register (IVARn)]
R/W halfword access
The interrupt vector register (IVAR0 to IVAR6) contains the lower 16 bits of the start address of the interrupt
handler for interrupts of the accepted level. This register is allocated between addresses x'20000000 to x'20000018
in the internal I/O space. The start address of interrupt levels 0 to 6 correspond to IVAR0 to IVAR6. When an
interrupt occurs, control is transferred to the address which is comprised of the upper 16 bits (x'4000) and the lower
16 bits (IVARn). This register is undefined when the system is reset.
Fig. 2-5-4 Interrupt Vector Address Register
0
0
15
0
14 13
12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
GN
0
IAGR
0
15
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
IVARn