Panasonic MN103001G/F01K - Manual (Page 72)

Extension Instruction Specifications
3-16
MACH (Signed half word data multiply-and-accumulate operation instruction: between registers)
[Instruction Format (Macro Name)]
MACH Dm, Dn
[Assembler Mnemonic]
udf30 Dm, Dn
[Operation]
This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension
function unit.
The instruction multiplies the contents of Dm (signed 16-bit integer: multiplicand) by the contents of Dn (signed
16-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the
upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and
it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower
32 bits in the multiply-and-accumulate register MCRL.
If an overflow from the 64-bit cumulative sum data is generated when the product is added to the cumulative sum,
multiply-and-accumulate overflow detection flag 1 is output to register MCVF.
[Flag Changes]
Flag Change Condition
V –
C –
N –
Z –
[Programming Cautions]
A non-extension instruction that consumes at least one cycle must be inserted between this instruction and the next
extension instruction.