Panasonic MN103001G/F01K - Manual (Page 358)

A/D Converter
14-4
14.3 Block Diagram
Fig. 14-3-1 The Block Diagram of A/D Converter
VREFH
1 2 4 8 16 32 64 128 256 512
ADCTR
ADnBUF
INC IOCLK
1
AN0
AN1
AN2
AN3
ADTRG
Selector
Data buffer
10 bit x 4 ch
Comparator
A/D interrupt request
Interrupt
generator
Divider
Shift registers for states
A/D conversion
trigger
Conversion reference
clock
Conversion
results
Conversion end
Results writing
Timer 2
underflow
Data buffer selection
For multiple-
channel
conversion
MC1 SC1 MC0 SC0 EN ST1 ST0 SHC CK1 CK0 MD1 MD0