Panasonic MN103001G/F01K - Manual (Page 155)

Bus Controller (BC)
8-41
8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode
8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to “0” in the corresponding memory control
register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0]
= "0" for the low-order byte and A[0] = "1" for the high-order byte. Word access (32 bits) is performed by means
of four accesses, with A[1:0] = "00", A[1:0] = "01", A[1:0] = "10", and A[1:0] = "11", starting from the low-order
side. Note that the low-order 8 bits (D7 to 0) are used for the data bus.
When using handshaking, bus access starts once synchronization with SYSCLK is achieved, and after the data
acknowledge signal (DK) is asserted, 2 MCLK cycles are consumed by the BC internally and then the access is
completed according to the specified parameters.
The various parameters for external memory access are set in memory control registers 2 and 3, corresponding to
each block.
Handshaking can only be set in synchronous mode.
Fig. 8-13-13 is the timing chart in the case of a half-word access using an “8-bit bus with handshaking, in synchronous
mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by
four.”
Fig. 8-13-14 is the timing chart in the case of a half-word access using an “8-bit bus with handshaking, in synchronous
mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by
two.”
Fig. 8-13-15 is the timing chart in the case of a half-word access using an “8-bit bus with handshaking, in synchronous
mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK.”
The DK signal connected to the microcontroller should be input so as to be asserted from point EA+DW onward,
and is negated before the next access.
Note that when writing, WE0 is asserted and the data is output on D7 to 0.
Note: If handshaking mode is set for memory block 3, the only settings that are permitted are those in which
MCLK is equal to SYSCLK multiplied by 4. Any setting in which MCLK is only twice SYSCLK, or in
which the two frequencies are equal, is prohibited.