Panasonic MN103001G/F01K - Manual (Page 377)

I/O Ports
15-11
Fig. 15-3-2 Port 1 Block Diagram (P11, and P10)
Internal data bus
M
P
X
P1OUT
P1nO
D1(n=1),
D0(n=0)
P1M
P1MD
P1DIR
P1nD
P... Represents one bit of each register.
M
P
X
P1PU
P1nI
P1IN
D7 to D0
Output enable
signal
P1n
(n=1,0)
RWSEL(n=1),
AS(n=0)
M
P
X
M
P
X
Address/data
multiplex mode
Control Signal
from BC