Panasonic MN103001G/F01K - Manual (Page 398)

I/O Ports
15-32
Fig. 15-7-4 Port 5 Block Diagram (P52, P50)
P5n
(n=2,0)
Internal data bus
P5OUT
P5DIR
P5nD
P5nO
P... Represents one bit of each register.
M
P
X
M
P
X
TM2IO(n=2),
SBO2(n=2),
SBO2 output enable (n=2),
SBT2 output enable (n=0)
M
P
X
P5nI
P5IN
TM2IO/SBO2(n=2),
TM0IO/SBT2(n=0)
TM0IO(n=0)
SBT2(n=0)
P5nM
P5MD
P5nS
P5SS