Panasonic MN103001G/F01K - Manual (Page 410)

I/O Ports
15-44
15.9.3 Pin Configurations
Table 15-9-1 shows the pin configurations for port 7.
Table 15-9-1 Port 7 Configuration
Port Pin P7n P7nM = "1" P7nM = "0"
No. P73S = "1" P73S = "0"
Port 7 55 P70 General-purpose output port CS0 Chip select signal 0 output
53 P71 General-purpose output port CS1 Chip select signal 1 output
or or
RAS1 * 1 DRAM RAS signal 1 output
52 P72 General-purpose output port CS2 Chip select signal 2 output
or or
RAS2 * 2 DRAM RAS signal 2 output
51 P73 General-purpose output port A23 Address output CS3 Chip select signal 3 output
[Note 1]
: When reset (whether in address/data separate mode or address/data multiplex mode)
*1 : If block 1 in the external memory space is not used as a DRAM space, CS1 is selected; if block 1 is used
as a DRAM space, RAS1 is selected.
*2 : If block 2 in the external memory space is not used as a DRAM space, CS2 is selected; if block 2 is used
as a DRAM space, RAS2 is selected.
Note: For details on the external memory space settings, refer to section 8.6, "Description of Registers."
[Note 2]
When the bus authority is granted, A23, CS3, CS2, RAS2, CS1, RAS1, and CS0 go to high impedance.