Panasonic MN103001G/F01K - Manual (Page 182)

Bus Controller (BC)
8-68
[Restrictions on Use]
(1) While software page mode is in effect, external access outside of the block in question is prohibited.
Cancel software page mode before accessing an external memory space other than the block for which software
page mode is set.
(2) While software page mode is in effect, the bus will not be released, regardless of any accesses to DRAM, even
if the bus request signal BR is asserted.
If it is necessary to accept the bus request signal BR while data is being transferred in software page mode,
partition the volume of data that is to be transferred in software page mode. Then, the program should temporarily
release software page mode once after the transfer of each block of data is completed. If the bus request signal
BR is being asserted when the software page mode is released, the bus grant signal BG is asserted, and the bus
is released.
(3) The DRAM refresh cycle is not performed while software page mode is in effect.
If DRAM refresh is necessary, temporarily release DRAM software page mode once within each refresh cycle.
(4) While software page mode is in effect, any access that writes a “1” to the PE bit of the memory control register
that initiated the mode is prohibited. (RASn remains asserted, and software page mode starts over again from
the output of the row address.)
8.14.4 DRAM refresh
If the REFE bit in the DRAM control register is set, CAS-before-RAS refresh is performed at the interval set by the
refresh count register. Fig. 8-14-7 illustrates the refresh operation concept. The refresh interval is the product of the
value of the REFCNT in the refresh count register. If the REFE bit in the DRAM control register is set, the refresh
count register operates as a down-counter, and the refresh count value is counted from REFC, the value of REFCNT,
to 0. The refresh operation is executed once in an idle external bus cycle during the period while the refresh count
value is counted down from REFC to 0. If, due to a serial interface access or other such operation, there is no idle
external bus cycle before the refresh count value reaches 0, then a refresh cycle is inserted right after the bus cycle
that is being executed at the moment the refresh count value reaches 0 is completed.
Fig. 8-14-8 shows the timing of a CAS-before-RAS refresh operation.
For details on the DRAM refresh interval setting, refer to section 8.6.6, "Refresh Count Register."