Panasonic MN103001G/F01K - Manual (Page 81)

Extension Instruction Specifications
3-25
MCST9 (Multiply-and-accumulate operation results 9-bit saturation operation instruction/positive value
conversion instruction)
[Instruction Format (Macro Name)]
MCST9 Dn
[Assembler Mnemonic]
udf03 Dn, Dn
[Operation]
When the 32-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate
register MCRL is equal to or greater than the maximum positive value for a 9-bit signed numeric value (0x000000ff),
the maximum positive value (0xff) is stored in Dn. If the value stored in the multiply-and-accumulate register
MCRL is equal to or less than the negative value for a 32-bit signed numeric value (0x00000000), the 0 (0x00) is
stored in Dn. In all other cases, the contents of MCRL are stored in Dn.
This instruction sets the contents of the multiply-and-accumulate operation overflow detect register MCVF in the
V flag.
[Flag Changes]
When multiply-and-accumulate operation overflow was not detected (MCVF = 0)
Flag Change Condition
V 0 Indicates that the multiply-and-accumulate operation is valid.
C 0 Always 0
N * Undefined
Z * Undefined
When multiply-and-accumulate operation overflow was detected (MCVF = 1)
Flag Change Condition
V 1 Indicates that the multiply-and-accumulate operation is invalid.
C 0 Always 0
N * Undefined
Z * Undefined
[Programming Cautions]
There is a one-instruction delay in the updating of the PSW to reflect flag changes.
However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in
the PSW.
When "udf03 Dm, Dn" is operated, Dm is ignored.
The operations of "udf03 imm8, Dn", "udf03 imm16, Dn" and "udf03 imm32, Dn" are not assured. In addition, a
system error interrupt does not occur in these cases.