Panasonic MN103001G/F01K - Manual (Page 147)

Bus Controller (BC)
8-33
8.13.1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode
Setting of the various parameters for external memory access is performed in memory control registers 0 to 3,
corresponding to each block. In synchronous mode, the bus access is initiated in synchronization with SYSCLK.
When fixed wait insertion is specified, the bus access ends to the timing set in the memory control register.
Fig. 8-13-1 is the timing chart in the case of a “16-bit bus with fixed wait states, in synchronous mode, in address/
data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.”
Fig. 8-13-2 is the timing chart in the case of a “16-bit bus with fixed wait states, in synchronous mode, in address/
data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.”
Fig. 8-13-3 is the timing chart in the case of a “16-bit bus with fixed wait states, in synchronous mode, in address/
data separate mode, and with the frequency of MCLK equal to that of SYSCLK.”
BCS indicates the timing during one SYSCLK cycle at which the access should start, and is expressed in terms of
the number of MCLK pulses since the rising edge of SYSCLK.
Note that when writing to byte 0, WE0 is asserted and the data is output on D7 to 0, and when writing to byte 1,
WE1 is asserted and the data is output on D15 to 8.
In addition, in the case of a word access (32 bits), the external access is performed twice with A[1] = "0" and A[1]
= "1".
Fig. 8-13-1 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
An
Dn
WEn
RE
CSn
EA
MCLK
SYSCLK
BCS BCE BCS BCE
REN
EA
WEN
Read Write
:Undefined