Panasonic MN103001G/F01K - Manual (Page 353)

Serial Interface
13-51
■ When a reception error is generated
• Transfer with 7-bit data length, parity on, and 2 stop bit
Fig. 13-4-7 Timing Chart (22)
When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends,
regardless of whether or not an error occurred.
When "reception end with error" is set as the reception interrupt source, an interrupt request is generated when
reception ends with an error having occurred. (An interrupt request is not generated at the moment that the error
occurred.)
An overrun error is generated when reception of the next data is completed before previously received data is read
from the SC3RXB. In this event, the previously received data is lost. The overrun error indicator flag (SC3OEF)
is updated at the moment the final data bit is received.
A parity error is generated when 0-fixed parity is set and a "1" is received, when 1-fixed parity is set and a "0" is
received, when even parity is set and an odd number of ones is received, or when odd parity is set and an even
number of ones is received. The parity error indicator flag (SC3PEF) is updated at the moment the parity bit is
received.
A feaming error is generated when "0" was received for the stop bit. The framing error indicator flag (SC3FEF) is
updated at the moment the stop bit is received.
■ Transmission interruption function
SC3TWS and SC3TWE in the SC3CTR serial 3 control register can be used to interrupt and resume transmissions
according to the status of external pin IRQ7.
A transmission is interrupted by masking the transmission end or transmission buffer empty interrupt.
The specifications of this microcontroller prohibit the writing of data to the transmission buffer when the interrupt
signal is masked through external pin control.
SP bp1 bp2 bp3 bp4 bp5 bp6 PTY bp0 ST SP
“H”
SC3RXF flag
SBI pin
SC3RBF flag
SC3OEF flag
SC3PEF flag
SC3FEF flag
Interrupt request