Panasonic MN103001G/F01K - Manual (Page 161)

Bus Controller (BC)
8-47
Fig. 8-13-18 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
Fig. 8-13-19 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
AS
CSn
ASA
ADE
RWSEL
MCLK
SYSCLK
BCS
A23* to 16
ADM15 to 0
RE
WEn EA
BCE BCS BCE
ASN
ASA
ADE
ASN
EA
REN WEN
Write Read
data in
addr addr
addr addr data out
“0”( ) “L”
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0”( ) “L”
AS
CSn
ASA
ADE
RWSEL
MCLK
SYSCLK
BCS=0
A23* to 16
ADM15 to 0
RE
WEn EA
BCE BCS=0 BCE
ASN
ASA
ADE
ASN
EA
REN WEN
Write Read
addr
data in addr
addr
addr data out
“0”( ) “L”
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0”( ) “L”