Panasonic MN103001G/F01K - Manual (Page 179)

Bus Controller (BC)
8-65
8.14.2 DRAM page mode
If the PAGE bit in the DRAM control register is set to “1”, page mode access is enabled, making high-speed access
in page mode possible for following accesses to DRAM.
(1) Word/half-word access when the bus width is set to 8 bits
(2) Word access when the bus width is set to 16 bits
Fig. 8-14-5 shows the page mode read timing and write timing.
(b) Write Timing
Fig. 8-14-5 DRAM Page Mode Read/Write Timing
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
(a) Read Timing
MCLK
An
RASn
CAS
RE
Dn
ASR
CAO
Row C olumn
CAS
RSH
C olumn
CAS
ASC ASC
MCLK
An
RASn
CAS
WE n
Dn
CAO
ASR
ASC
CAS
C olumn
ASC
RSH
C olumn
CAS
Row