Panasonic MN103001G/F01K - Manual (Page 187)

Bus Controller (BC)
8-73
8.16 Cautions
These cautions concern the BC. These cautions must be heeded, since failure to do so may result in misoperation.
1. Do not change the contents of the relevant memory control register and the DRAM control register while
accessing external memory space, except when software page mode is not in effect.
2. Do not overwrite the refresh counter register while the REFE bit is “1” in the DRAM control register.
3. “0” is output on pins A23* to 16 when pins ADM15 to 0 are operating as data pins in address/data multiplex
mode, as shown in the diagram below; as a result, in order to use pins A23* to 16 while pins ADM15 to 0 are
operating as data pins, it is necessary to latch the output on pins A23* to 16 with the address strobe AS.
*: A23 also serves as CS3.
Fig. 8-16-1 Example of Address Pin Usage in Address/Data Multiplex Mode
4. When entering the stop mode, the output mode of pins ADM15 to 0 is undefined. Therefore, when pins
ADM15 to 0 are being pulled up according to the I/O port output mode register setting, the pull-up setting for
pins ADM15 to 0 should be released before entering the stop mode in order to avoid power consumption in the
stop mode due to the pull-up resistance.
Note: For details on the output mode register settings, refer to Chapter 15, “I/O Ports.”
5. Interrupts are prohibited and the bus is locked (occupied by the CPU) when executing BSET or BCLR, however,
if a BSET or BCLR instruction is executed during program execution in external memory, a bus authority
release due to an external bus request may be interposed between the data read and data write by the BSET or
BCLR instruction.
If the atomic bus cycles (i.e. bus lock) of the BSET or BCLR instruction need to be guaranteed in a system that
uses multiple processors, either of the following measures should be taken.
1. A program in which a BSET or BCLR instruction is executed should be placed in internal memory.
Latched
AS
CSn
MCLK
SYSCLK
ADM15 to 0
ASA
ADE
A23* to 16
A23* to 16
BCS
BCE
ASN
“0” (low level)
data
addr
addr
addr
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z