Panasonic MN103001G/F01K - Manual (Page 18)

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Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ................ 8-49
Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK) ......................................... 8-50
Fig. 8-13-23 Access Timing on a 16-bit Bus in Asynchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) ................ 8-51
Fig. 8-13-24 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) ................ 8-53
Fig. 8-13-25 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ................ 8-54
Fig. 8-13-26 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK) ......................................... 8-55
Fig. 8-13-27 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) ................ 8-57
Fig. 8-13-28 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ................ 8-58
Fig. 8-13-29 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK) ......................................... 8-59
Fig. 8-13-30 Access Timing on a 8-bit Bus in Asynchronous Mode and
in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) ................ 8-61
Fig. 8-14-1 DRAM Access Timing Chart .................................................................................. 8-62
Fig. 8-14-2 Case Where the RAS Precharge Interval is at Its Minimum
(Example Where RP = 1 and ASR = 1) ................................................................... 8-63
Fig. 8-14-3 Example of an 8-bit Data Write Using 2 WE Control (16-bit Bus Width) ............. 8-64
Fig. 8-14-4 Example of an 8-bit Data Write Using 2 CAS Control (16-bit Bus Width) ........... 8-64
Fig. 8-14-5 DRAM Page Mode Read/Write Timing .................................................................. 8-65
Fig. 8-14-6 Software Page Mode Read/Write Timing ............................................................... 8-67
Fig. 8-14-7 DRAM Refresh Operation ....................................................................................... 8-69
Fig. 8-14-8 DRAM Refresh Timing ........................................................................................... 8-69
Fig. 8-15-1 Bus Arbitration Timing 1
(Bus Authority Release/Bus Authority Acquisition, nfr = 4) .................................. 8-71
Fig. 8-15-2 Bus Arbitration Timing 2
(Bus Authority Release/Bus Authority Acquisition, nfr = 2) .................................. 8-71
Fig. 8-15-3 Bus Arbitration Timing 3
(Bus Authority Release/Bus Authority Acquisition, nfr = 1) .................................. 8-72
Fig. 8-15-4 Bus Arbitration Timing 4
(Refresh Request Generated While Bus Authority Has Been Released) ................ 8-72
9. Interrupt Controller
Fig. 9-3-1 System Diagram ........................................................................................................ 9-2
Fig. 9-4-1 Block Diagram 1 ....................................................................................................... 9-3
Fig. 9-4-2 Block Diagram 2 ....................................................................................................... 9-4
Fig. 9-4-3 Block Diagram 3 ....................................................................................................... 9-5