Panasonic MN103001G/F01K - Manual (Page 457)

Errors Page Corrections Page
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- External interrupts: 9 sources (8 individual IRQs, and 1 external NMI)
_________
(The column of "Pin Function" such as "Pin name" is "NMIRQ" in the table.)
External NMI input
(Note) Interrupts are prohibited and the bus is locked (occupied by
the CPU) when executing BSET or BCLR.
(In the figure)
(In the table 2-5-1)
Interrupt prohibited (only NMI accepted)
(In the 4th line of [Interrupt Control Registers(GnICR)] )
Register G0ICR is dedicated for NMI interrupts, and ...
(In the 9th line of [Interrupt Accept Group Register(IAGR)] )
Accessing IAGR is meaningless during NMI interrupts.
(In the 2nd line of "External pin non-maskable interrupt")
..., the external NMI request flag (NMIF) in the...
(The 1st line of "System error interrupt")
System error interrupt occurs when an unimplemented instruction is
executed or other fatal error occurs.
( Interrupt processing sequences executed by the hardware )
1. The PC (return address) is saved to the stack (SP-4).
2. The PSW is saved to the stack (SP-8).
(In the 4th line of " Interrupt processing sequences executed by the hardware ")
(IM2 to IM0 is undefined in case of NMI.)
(In the number 3 of " Example of pre-processing by the interrupt handler " )
* In case of NMI, ...
The correction table in The Revised Edition of MN103001G/F01K LSI User's Manual
(From 2nd Edition (or 2nd Edition 1st printing) to 5th Edition)
Reset interrupt
Non-maskable interrupt Reset interrupt
NMI interrupt
_____________
- External interrupts: 9 sources (IRQn (n=7 to 0) x 8, and NMIRQ x 1 )
_________
(The column of "Pin Function" such as "Pin name" is "NMIRQ" in the table.)
External non-maskable interrupt input
(Following sentence is added.)
If the CPUM register is accessed to make a transition to an operating
mode of SLEEP/HALT/STOP during execution of a program in external
memory, a branch instruction should not be located within the three
instructions immediately following the CPUM register access instruction.
Note :
Interrupts are prohibited and the bus is locked (occupied by the CPU)
when executing BSET or BCLR, however, if a BSET or BCLR
instruction is executed during program execution in external memory,
a bus authority release due to an external bus request may be interposed
between the data read and data write by the BSET or BCLR instruction.
If the atomic bus cycles (i.e. bus lock) of the BSET or BCLR instruction
need to be guaranteed in a system that uses multiple processors, either
of the following measures should be taken.
1. A program in which a BSET or BCLR instruction is executed should
be placed in internal memory.
_____
2. Designate the bus authority request pin (BR) as a general-purpose
_____
input port, and the bus authority release pin (BG) as a general-purpose
output port, for instance, so that bus requests cannot be accepted during
execution of a BSET or BCLR instruction.
(In the figure)
(In the table 2-5-1)
Interrupt prohibited (only non-maskable interrupts accepted)
(In the 4th line of [Interrupt Control Registers(GnICR)] )
Register G0ICR is dedicated for non-maskable interrupts, and ...
(In the 9th line of [Interrupt Accept Group Register(IAGR)] )
Accessing IAGR is meaningless during non-maskable interrupts.
(In the 2nd line of "External pin non-maskable interrupt")
..., the external non-maskable interrupt request flag (NMIF) in the...
(The 1st line of "System error interrupt")
System error interrupt occurs when an unaligned memory access or an
unimplemented instruction is executed or other fatal error occurs.
(Following note is added.)
Note: Do not change the interrupt enable (IE) in PSW during
non-maskable interrupt processing.
( Interrupt processing sequences executed by the hardware )
1. The PSW is saved to the stack (SP-8).
2. The PC (return address) is saved to the stack (SP-4).
(In the 4th line of " Interrupt processing sequences executed by the hardware ")
(IM2 to IM0 is undefined in case of non-maskable interrupts.)
(In the number 3 of " Example of pre-processing by the interrupt handler " )
* In case of non-maskable interrupts, ...
( [Programming Cautions] is added for PUTX.)
(Following sentences are added to [Programming Cautions] of GETX.)
When "udf15 Dm, Dn" is operated, Dm is ignored.
The operations of "udf15 imm8, Dn", "udf15 imm16, Dn" and "udf15
imm32, Dn" are not assured. In addition, a system error interrupt does
not occur in these cases.