1 operation extension function, 2 3.1 operation extension function, Extension instruction specifications – Panasonic MN103001G/F01K User Manual

Page 58

Advertising
background image

Extension Instruction Specifications

3-2

3.1

Operation Extension Function

The MN1030 series 32-bit microcontrollers are provided with 32 extension instructions which can be defined by
users. This allows the desired processing to be performed at high speed for each model expansion by assigning
multiply, multiply-accumulate, saturation and other application-oriented operations to extension instructions and
connecting extension function unit via the extension operation interface of the CPU core.

Extension instructions include instructions UDF00 to UDF15 which transfer register or immediate values to the

extension function unit and load the operation results to the data register, and instructions UDF20 to UDF35 which

only transfer register to the extension function unit. Processing which performs user-defined operations is assigned

to instructions UDF00 to UDF15, and processing which only transfers data to the extension function unit is assigned

to instructions UDF20 to UDF35. Extension operations which require three or more inputs can be realized by

transferring the input data to the extension function unit beforehand using instructions UDF20 to UDF35 and then

performing the operation using instructions UDF00 to UDF15.

The block diagram showing extension function unit connected to the CPU for this series is as follows.

This microcontroller has a 32 x 16 multiplier, priority encoder, and saturation compensation unit on chip. The

extension functions that use the extension function unit are explained in section 3.2, "Extension Instructions."

Fig. 3-1-1 Block Diagram of the Extension Function Unit

......

......

......

Operation

extension block B

Operation

extension block A

User

extension

instruction

decoder B

User

extension

instruction

decoder A

User extension

function unit

B

User extension

function unit

A

AU

LU

CPU

instruction

decoder

Instruc-

tion

queue

Instruction decoding

block

Barrel
shifter

Program

counter

block

Register

Operand address

Instruction

address

Operand data

Instruction

data

Operation extension interface

Advertising