Panasonic MN103001G/F01K - Manual (Page 53)

2-19
CPU
[Level interrupts]
Level interrupts are interrupts for which the interrupt level can be controlled through the interrupt enable (IE) and
interrupt mask (IM2 to IM0) bits in the PSW. Level interrupts are interrupts from the interrupt group controllers
external to the CPU (in other words, peripheral interrupts). There are 18 groups, or 35 interrupt factors.
Each interrupt group controller includes an interrupt control register (GnICR); the interrupt priority level can be set
independently for each interrupt group. It is also possible to set the same interrupt priority level for different
interrupt groups. If interrupts of the same priority level are generated simultaneously, the interrupts are accepted in
the sequence set by the hardware (the lower the interrupt group number, the higher the priority).
When a level interrupt is accepted, the hardware causes the program to branch to an address with the upper 16 bits
being "x'4000" and the lower 16 bits indicated by the interrupt vector address register IVARn corresponding to the
interrupt level.
The interrupt handler accesses IAGR to analyze the interrupt group, accesses GnICR (n = 2 to 19) to analyze the
interrupt factor, performs interrupt processing, cancels the interrupt factor, and then returns to the normal program
using the RTI instruction.
2.5.4 Interrupt Definition
When this microcontroller accepts an interrupt, first the sequences automatically processed by the hardware are
executed. Then control transfers to interrupt handler by the software and the interrupt handler is started up.
The interrupt processing sequences are described below.
(Interrupt processing sequences executed by the hardware)
1. The PSW is saved to the stack (SP-8).
2. The PC (return address) is saved to the stack (SP-4).
3. The PSW is updated.
IE is cleared and the accepted interrupt level is set in IM2 to IM0. (IM2 to IM0 is undefined in case of non-
maskable interrupts.)
4. The stack pointer is updated. (SP-8 → SP)
5. Control is transferred to the address corresponding to the accepted interrupt factor or the address comprised of
the interrupt vector address register (IVARn).
When an interrupt other than a reset interrupt is accepted, control is transferred to the address corresponding to the
interrupt factor or the address comprised of the interrupt vector address register. The processing listed below is then
performed at the branch destination in order to judge the interrupt factor in further detail.
See "2.5.3 Interrupt Types" for processing reset interrupts.
(Note) In General, Branch instructions (JMP instruction, etc.) are placed at the branch destination for reset interrupts,
then it branches to the initialization program.