Panasonic MN103001G/F01K - Manual (Page 376)

I/O Ports
15-10
15.3 Port 1
15.3.1 Block Diagram
Figs. 15-3-1 and 15-3-2 show block diagrams for port 1.
Fig. 15-3-1 Port 1 Block Diagram (P17 to P12)
Internal data bus
M
P
X P1n
(n=7,6,5,4,3,2)
P1OUT
D7(n=7)
to D2(n=2)
P1M
P1MD
P1DIR
P1nD
P1nO
P... Represents one bit of each register.
M
P
X
P1PU
P1nI
P1IN
D7 to D0
Output enable
signal