Panasonic MN103001G/F01K - Manual (Page 191)

Interrupt Controller
9-3
9.4 Block Diagram
Fig. 9-4-1 Block Diagram 1
Interrupt control
register address
NMIRQ pin
Watchdog timer overflow
System error
Reserved for system
Timer 0 underflow
Timer 1 underflow
Timer 2 underflow
Timer 3 underflow
Timer 4 underflow
Timer 5 underflow
Timer 6 underflow
Timer 7 underflow
Timer 8 underflow
Timer 9 underflow
Timer A underflow
Timer B underflow
Timer 10 overflow
Timer 10 compare/capture A
Timer 10 compare/capture B
—
Timer 11 underflow
Timer 12 underflow
Timer 13 underflow
—
The interrupt level can be set separately for
each group. (However, GROUP 0 and
GROUP 1 are non-maskable.)
CPU core
GROUP
2
3
2
1
0
GROUP
3
3
2
1
0
x'3400010C
x'34000110
GROUP
4
3
2
1
0
GROUP
5
3
2
1
0
x'34000114
Non-maskable
interrupts
Level: 0 to 6
GROUP
1
3
2
1
0
GROUP
0
3
2
1
0
x'34000100
—
x'34000108
GROUP
6
3
2
1
0
x'34000118