Panasonic MN103001G/F01K - Manual (Page 106)

Operating Mode
5-4
5.3 Low Power Mode
Low power consumption is achieved by stopping the oscillation of the oscillators and the clock generator (CG) and
stopping the clocks supplied to the CPU and peripheral circuits. Low power mode contains the following three
modes and transitions to the three modes are made through software.
Stop mode (STOP)
In this mode, the oscillation of oscillators as well as the CG oscillation are stopped. In the STOP mode,
oscillator and CG operation is started by an interrupt and the microcontroller changes to normal operation
mode (NORMAL) after waiting for oscillation to be stabilized.
Halt mode (HALT)
In this mode, the oscillators and CG are oscillating but clock supply to the CPU and peripheral circuits is
stopped. Thus, CPU and peripheral circuits operation is stopped.
In the HALT mode, the microcontroller changes to normal operation mode (NORMAL) when an interrupt
occurs.
Sleep mode (SLEEP)
In this mode, the oscillators and CG are oscillating but clock supply only to the CPU is stopped. Thus, CPU
operation is stopped but the peripheral circuits are operating. In SLEEP mode, the microcontroller changes
to normal operation mode (NORMAL) when an interrupt occurs.
■ Operation of various peripheral functions in the low power consumption modes
The operation of the peripheral functions in SLEEP, HALT, and STOP mode is shown in the table below.
In SLEEP mode, all peripheral functions operate except for the bus controller and the watchdog timer. In
HALT and STOP mode, most peripheral functions are stopped.
In SLEEP mode, the interrupt controller accepts interrupt requests from the peripheral blocks and external pin
interrupt requests, notifies the CPU core, and then initiates recovery from SLEEP mode. In HALT/STOP
mode, the interrupt controller accepts the external pin interrupt request, notifies the CPU core, and then initiates
recovery from HALT/STOP mode.
When making a transition to HALT/SLEEP mode, stop the watchdog timer by clearing the WDCNE bit to "0"
in watchdog timer control register WDCTR.
SLEEP HALT STOP
Bus controller
Only responds to DRAM refresh
Stopped Stopped
and external bus requests
Interrupt controller Operates Operates Operates
8-bit timer Operates Stopped Stopped
16-bit timer Operates Stopped Stopped
Watchdog timer Stopped Stopped Stopped
Serial interface Operates Stopped Stopped
A/D converter Operates Stopped Stopped