Panasonic MN103001G/F01K - Manual (Page 151)

Bus Controller (BC)
8-37
An
Dn
WEn
RE
CSn
EA
MCLK
SYSCLK
EA
Read Write
BCE BCE
REN
WEN
: Undefined
8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode
Asynchronous mode is used for accessing external memory at high speed; the address signals, CSn signals, etc., are
output asynchronously with the SYSCLK but in synchronization with the internal MCLK. In asynchronous mode,
accesses are all by fixed wait insertion.
Fig. 8-13-7 is the timing chart in the case of a “16-bit bus in asynchronous mode, in address/data separate mode,
and with the frequency of MCLK equal to that of SYSCLK multiplied by four.”
Fig. 8-13-8 is the timing chart in the case of a “16-bit bus in asynchronous mode, in address/data separate mode,
and with the frequency of MCLK equal to that of SYSCLK multiplied by two.”
Fig. 8-13-9 is the timing chart in the case of a “16-bit bus in asynchronous mode, in address/data separate mode,
and with the frequency of MCLK equal to that of SYSCLK.”
During a read, the RE signal is asserted at EA x MCLK after the start of the bus cycle. During a write, the WE
signal is asserted at EA x MCLK after the start of the bus cycle.
Note that when writing to byte 0, WE0 is asserted and the data is output on D7 to 0, and when writing to byte 1,
WE1 is asserted and the data is output on D15 to 8.
In addition, in the case of a word access (32 bits), the external access is performed twice with A[1] = "0" and A[1]
= "1".
Fig. 8-13-7 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data
Separate Mode (MCLK = SYSCLK multiplied by 4)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”