Panasonic MN103001G/F01K - Manual (Page 301)

Watchdog Timer
12-9
Watchdog operation
If the WDCNE flag is set to "1" and the watchdog operation is enabled, a non-maskable interrupt is generated if a
watchdog timer overflow occurs.
When an overflow occurs, the watchdog timer overflow output is output to the WDOVF flag. Pulse output or level
output can be selected through the WDOVT flag. When level output is selected, the watchdog timer overflow
output (WDOVF flag) is cleared by writing a "1" to the WDRST flag or by reset (RST) pin "L" level input.
Fig. 12-5-3 Operation Diagram 3: Watchdog Operation
Before setting the WDCNE flag to "1", write a "1" to the WDRST flag to reset the counter.
When switching to HALT or SLEEP mode, set the WDCNE flag to "0" to turn off the watchdog timer.
Self-reset operation
The chip resets internally when a "1" is written to the CHIPRST bit in the RSTCTR register. The oscillation
stabilization wait operation is not performed.
The reset generated by writing the CHIPRST flag is an internal reset signal within the chip and does not manifest
itself on the external reset pin (RST pin).
Watchdog timer
count value
Overflow
4.369 ms to 1118.481 ms
(when CKSEL = “H” and the oscillating input
frequency is 15 MHz)
Counter reset by writing
“1” to the WDRST flag
Non-maskable interrupt
WDOVF flag output
(when pulse output is
selected)
WDOVF flag output
(when level output is
selected)
SYSCLK 255-cycle width
Reset by writing a “1”
to the WDRST flag, or
by reset pin input