Panasonic MN103001G/F01K - Manual (Page 139)

Bus Controller (BC)
8-25
Notes when switching the internal clock multiplier
Be aware of the following points when setting the clock control register CKCTR and changing the internal clock
multiplier.
• If external memory is accessed immediately after setting the clock control register CKCTR, the multiplier for
the internal clock MCLK may change in the middle of the access, resulting in a change in the external bus
timing.
The internal clock multiplier changes during an external memory access in any of the following cases:
(1) When executing a program in internal instruction memory, the internal clock multiplier changes in the event of
an access initiated by an external memory access instruction that came within seven instructions after an
instruction that writes to the clock control register CKCTR.
(2) When executing a program in external memory, the internal clock multiplier changes in the event of either an
instruction read or an access initiated by an external memory access instruction, when either came within three
instructions after an instruction that writes to the clock control register CKCTR.
(3) When interrupt processing is generated immediately after writing CKCTR and the stack pointer is pointing to
the external memory space, the internal clock multiplier changes for the first write access to the stack immediately
after the interrupt is accepted.
Use either of the following methods in response to the above situations:
Method 1: In situations where it does not matter if the clock multiplier changes during the external memory
access
Write CKCTR after setting the bus controller for the external memory access to a value that permits external
memory access with any clock multiplier before or after overwriting CKCTR.
Method 2: In situations where the clock multiplier must not change during the external memory access
(limited to memory extension mode)
Overwrite CKCTR through a program in internal instruction memory, and then place at least seven instructions that
do not access external memory (for example, nop instructions) after the instruction that writes CKCTR. In addition,
if there is a possibility that an interrupt request may be generated immediately after the CKCTR write operation,
either set the stack pointer in internal data RAM beforehand, or else prohibit the acceptance of interrupts before
writing CKCTR.
Note that method 2 cannot be used in processor mode; use method 1.