Panasonic MN103001G/F01K - Manual (Page 170)

Bus Controller (BC)
8-56
8.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode
By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex
pins for the memory address and memory data signals (pins ADM15 to 0).
8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to “0” in the corresponding memory control
register.
In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for
the low-order byte and A[0] = “1” for the high-order byte. Note that the low-order 8 bits (D7 to 0) are used for the
data bus. Word access (32 bits) is performed by means of four accesses, with A[1:0] = “00”, A[1:0] = “01”, A[1:0]
= “10”, and A[1:0] = “11”, starting from the low-order side.
With handshaking, bus access commences in synchronization with SYSCLK, and after the data acknowledge signal
(DK) is asserted, two MCLK cycles are consumed by the BC internally, and then access is completed as per the
designated parameters.
The various parameters for external memory access are set in memory control registers 2 and 3, corresponding to
each block.
Fig. 8-13-27 is the timing chart in the case of a half-word access using an “8-bit bus with handshaking, in address/
data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.”
Fig. 8-13-28 is the timing chart in the case of a half-word access using an “8-bit bus with handshaking, in address/
data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.”
Fig. 8-13-29 is the timing chart in the case of a half-word access using an “8-bit bus with handshaking, in address/
data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK.”
As shown in each timing chart, the ADM15 to 0 pins go to “Hi-Z” or the undefined output state while CSn is
negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled
up or go to “Hi-Z”, depending on the setting of the I/O port output mode register.
The DK signal connected to the microcontroller should be input so as to be asserted from point EA+DW onward,
and is negated before the next access.
Note that when writing, WE0 is asserted and the data is output on ADM7 to 0.
Note: For details on the mode settings, refer to Table 8-9-1, “Mode Settings by the BC External Pins.”
Note: If handshaking mode is set for memory block 3, the only settings that are permitted are those in which
MCLK is equal to SYSCLK multiplied by 4. Any setting in which MCLK is only twice SYSCLK, or in
which the two frequencies are equal, is prohibited.
Note: “0” (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as
data pins. Therefore, refer to 3. in section 8.16, “Cautions,” regarding the use of these pins.