Panasonic MN103001G/F01K - Manual (Page 236)

8-bit Timers
10-16
Timer n base register (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
Register symbol: TMnBR
Address: x'34001010 (n = 0), x'34001011 (n = 1), x'34001012 (n = 2),
x'34001013 (n = 3), x'34001014 (n = 4), x'34001015 (n = 5),
x'34001016 (n = 6), x'34001017 (n = 7), x'34001018 (n = 8),
x'34001019 (n = 9), x'3400101A (n =A), x'3400101B (n = B)
Purpose: This register sets the initial value of the timer n binary counter and the underflow cycle.
Bit No. 7 6 5 4 3 2 1 0
Bit TMn TMn TMn TMn TMn TMn TMn TMn
name BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
Reset 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
The value that is set in TMnBR is loaded into TMnBC under the following conditions:
(1) When TMnLDE = 1
(2) When an underflow has occurred
TMnBC generates an underflow interrupt every (value set in TMnBR + 1) counts.
When PWM output has been selected for timers 4 to B, the PWM output cycle is set.
Timer n binary counter (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
Register symbol: TMnBC
Address: x'34001020 (n = 0), x'34001021 (n = 1), x'34001022 (n = 2),
x'34001023 (n = 3), x'34001024 (n = 4), x'34001025 (n = 5),
x'34001026 (n = 6), x'34001027 (n = 7), x'34001028 (n = 8),
x'34001029 (n = 9), x'3400102A (n = A), x'3400102B (n = B)
Purpose: This register is the binary counter for timer n. The counter value can be read from this register.
Bit No. 7 6 5 4 3 2 1 0
Bit TMn TMn TMn TMn TMn TMn TMn TMn
name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Reset 0 0 0 0 0 0 0 0
Access R R R R R R R R
This is a down counter.
The initial value for this register is the value that is set in TMnBR, and this register generates an underflow and an
interrupt request every (value set in TMnBR + 1) counts.