Panasonic MN103001G/F01K - Manual (Page 47)

2-13
CPU
• Bit instructions
BTST Bit Test
BSET Test and set (processing unit: byte)
BCLR Test and clear (processing unit: byte)
• Shift instructions
ASR Shift Right Arithmetic
LSR Shift Right Logical
ASL Shift Left Arithmetic
ASL2 Shift Left 2-bit Arithmetic
ROR Rotate 1 bit to the right
ROL Rotate 1 bit to the left
• Branch instructions
Bcc Branch on condition codes (PC relative)
Lcc Loop on condition codes (PC relative)
SETLB Set loop buffer
JMP Unconditional branch (PC relative, register indirect)
CALL Subroutine call (Advanced function)
CALLS Subroutine call
RET Return from subroutine (Advanced function)
RETF Return from subroutine (Advanced function, high-speed)
RETS Return from subroutine
RTI Return from interrupt program
TRAP Subroutine call to specified address
NOP No operation
• Extension instructions
UDF User extension instruction (sign-extension)
UDFU User extension instruction (zero-extension)
Note:
Interrupts are prohibited and the bus is locked (occupied by the CPU) when executing BSET or BCLR, however, if
a BSET or BCLR instruction is executed during program execution in external memory, a bus authority release due
to an external bus request may be interposed between the data read and data write by the BSET or BCLR instruction.
If the atomic bus cycles (i.e. bus lock) of the BSET or BCLR instruction need to be guaranteed in a system that uses
multiple processors, either of the following measures should be taken.
1. A program in which a BSET or BCLR instruction is executed should be placed in internal memory.
2.
_____
Designate the bus authority request pin (BR) as a general-purpose input port, and the bus authority release pin
_____
(BG) as a general-purpose output port, for instance, so that bus requests cannot be accepted during execution of
a BSET or BCLR instruction.