Panasonic MN103001G/F01K - Manual (Page 357)

A/D Converter
14-3
14.2 Features
• S/H Built in
• Conversion accuracy
10 bits
±
5 LSB (Linearity error)
The value of VREFH divided into 1024 steps is stored in AD0BUF to AD3BUF.
• Conversion reference clock
Selectable from 1/2, 1/4, 1/8, or 1/16 of IOCLK
Set this parameter so that one cycle is at least 200 ns.
(Example: When IOCLK is 15 MHz, set this parameter 1/4 or 1/8 or 1/16.)
• Number of sampling cycles
Select either two or four conversion reference clock cycles.
Set this parameter so that the sampling cycle is at least 400 ns.
• Conversion time 2.8
µ
s/channel
(When IOCLK is 10 MHz; conversion reference clock is 1/2 of IOCLK and the
number of sampling cycles is 2 cycles)
3.74
µ
s/channel
(When IOCLK is 15 MHz; conversion reference clock is 1/4 of IOCLK and the
number of sampling cycles is 2 cycles)
• Operating modes 14 modes
Channel 0 one-time conversion, Channel 0 continuous conversion
Channel 1 one-time conversion, Channel 1 continuous conversion,
Channel 0 to 1 one-time conversion, Channel 0 to 1 continuous conversion
Channel 2 one-time conversion, Channel 2 continuous conversion,
Channel 0 to 2 one-time conversion, Channel 0 to 2 continuous conversion
Channel 3 one-time conversion, Channel 3 continuous conversion,
Channel 0 to 3 one-time conversion, Channel 0 to 3 continuous conversion
• Conversion start 1) Timer 2 underflow
2) Trigger input (falling edge) to external pin (ADTRG pin)
3) Register setting by instruction
• Interrupts An interrupt request is generated when a conversion is completed on one channel
or on one series of channels.