Panasonic MN103001G/F01K - Manual (Page 82)

Extension Instruction Specifications
3-26
MCST48 (Multiply-and-accumulate operation results 48-bit saturation operation instruction)
[Instruction Format (Macro Name)]
MCST48 Dn
[Assembler Mnemonic]
udf06 Dn, Dn
[Operation]
When the 64-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate
registers MCRH and MCRL is equal to or greater than the maximum positive value for a 48-bit signed numeric
value (0x00007fffffffffff), the maximum positive value (0x00007fffffffffff) is output and bits 47 through bits 16 of
that output are stored in Dn. If the value stored in the multiply-and-accumulate registers MCRH and MCRL is
equal to or less than the maximum negative value for a 48-bit signed numeric value (0xffff800000000000), the
maximum negative value (0xffff800000000000) is output and bits 47 through bits 16 of that output are stored in
Dn. In all other cases, the contents of MCRH and MCRL are output and bits 47 through bits 16 of that output are
stored in Dn.
This instruction sets the contents of the multiply-and-accumulate operation overflow detect register MCVF in the
V flag.
[Flag Changes]
When multiply-and-accumulate operation overflow was not detected (MCVF = 0)
Flag Change Condition
V 0 Indicates that the multiply-and-accumulate operation is valid.
C 0 Always 0
N * Undefined
Z * Undefined
When multiply-and-accumulate operation overflow was detected (MCVF = 1)
Flag Change Condition
V 1 Indicates that the multiply-and-accumulate operation is invalid.
C 0 Always 0
N * Undefined
Z * Undefined
[Programming Cautions]
There is a one-instruction delay in the updating of the PSW to reflect flag changes.
However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in
the PSW.
When "udf06 Dm, Dn" is operated, Dm is ignored.
The operations of "udf06 imm8, Dn", "udf06 imm16, Dn" and "udf06 imm32, Dn" are not assured. In addition, a
system error interrupt does not occur in these cases.