Panasonic MN103001G/F01K - Manual (Page 67)

Extension Instruction Specifications
3-11
MULQ (Signed high-speed multiplication instruction: between registers)
[Instruction Format (Macro Name)]
MULQ Dm, Dn
[Assembler Mnemonic]
udf00 Dm, Dn
[Operation]
This instruction performs multiplication quickly using the multiplier of the extension function unit.
The contents of Dm (signed 32-bit integer: multiplicand) and Dn (signed 32-bit integer: multiplier) are multiplied,
and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower
32 bits into Dn.
The significant value range of the multiplicand stored in Dm before the operation is judged (starting point: LSB,
judgment unit: 2 bytes), and the operation is only performed for the range containing these significant values. In
other words, the smaller the absolute value of the contents stored in Dm, the quicker operation results can be
obtained.
[Flag Changes]
Flag Change Condition
V * Undefined
C * Undefined
N + 1 when MSB of the lower 32 bits of the results is 1; 0 in all other cases
Z + 1 when the lower 32 bits of results are 0; 0 in all other cases
[Programming Cautions]
PSW updating by flag changes is delayed by one instruction.
However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.