Panasonic MN103001G/F01K - Manual (Page 145)

Bus Controller (BC)
8-31
8.12 Accessing the Internal I/O Space
Accesses to the internal I/O space (I/O register) are performed through the I/O bus, with the bus controller controlling
the interface for read/write requests from the CPU. Accesses between the bus controller and the internal I/O space
are executed in synchronization with IOCLK. Fig. 8-12-1 shows the timing chart when accessing the internal I/O
space.
Fig. 8-12-1 Internal I/O Space Access
During a read, the address and the read request signal (RR) are output in synchronization with the rising edge of
IOCLK. After MCLK 1 cycle, the data strobe signals (DSn) are asserted, and the I/O side begins to drive the data
on the data bus. During a write, the address and the write request signal (WR) are output in synchronization with
the falling edge of IOCLK. After MCLK 1 cycle, the data strobe signals (DSn) are asserted, and are then negated
1/4 of an IOCLK cycle before the end of the I/O access cycle. The write is performed at the rising edge of the DSn
signals.
MCLK
IOCLK
I/O Bus
Address
WR
RR
DSn
Write Read
I/O Bus
Data