Panasonic MN103001G/F01K - Manual (Page 224)

8-bit Timers
10-4
Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B)
Output waveform
control
Timer n
(n = 4, 5, 6, 7, 8, 9, A, B)
Match
Output control
TMnOUT
Compare register
Compare register
buffer
TMnBR
TMnBC
CK0 CK1 LDE CNE
TMnMD
TMnIN0
TMnIN1
TMnIN2
TMnIN3
TMnCI
TMnCLK
TMnIRQ
TMnCO
CK2
TMnIN5
TMnIN6
TMnIN7
TMnIN4
OM0 OM1 —
TMnCMP
Compare register
Underflow
Reload
Load
Cascaded signal from
higher order timer
Underflow interrupt
Timer output
Cascaded signal
Count operation
enabled
mode register
base register
binary counter
Clock output
Reload Load