Altera JNEye - Manual (Page 152)

Tutorial: PCI Express 8GT
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2015.05.04
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This tutorial uses JNEye to run a link simulation. This example and its associated channel models are
provided with the JNEye distribution. The configuration file Demo.jne (included in the software distribu‐
tion) contains the same link topology and a majority of the link settings discussed in this tutorial.
In this tutorial, a link that approximates a typical PCI-Express 8GT system with an Altera Stratix V GX
transmitter and a generic PCI-Express 8GT receiver is built and simulated in JNEye. The following figure
shows the link topology.
Note: This link configuration and simulation are for demonstration purposes. It is not intended for
actual implementation. Consult Altera design guidelines for actual high-speed link design and
implementation.
Figure 3-1: Example of PCI-Express 8GT Link Topology
Related Information
Link and Simulation Setting on page 2-6
The Link and Simulation Setting tab sets the global link parameters and simulation configurations.
Methodology
This simulation emulates an Altera Stratix V GX transmitter (with embedded package model), a PCI
Express 8GT receiver (with embedded package model), and a ~18-inch backplane channel. Per PCI
Express 8GT specifications, the link operates at 8 Gbps with a bit error rate (BER) < 10 –12 . The transmitter
must have a minimum differential output voltage of 800 mV and a rise/fall time of ~35 ps (at 0.8 V V
OD
).
In this simulation, the Stratix V GX transmitter is set to 800 mV V
OD
(VOD level = 40). Additionally, the
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