Altera JNEye - Manual (Page 25)

Test Point Options
JNEye provides the following default test point options:
• Data Latch Only—(default option) Simulation results at the data latch will be saved and displayed.
Data latch can be at DFE output, CTLE output, or input stage of receiver depending on the link or
device configuration. Custom test points will be neglected and the simulation results at test points will
not be shown.
• TX/Channel/CTLE-/DFE-Latch—JNEye automatically sets up to four test points for the link:
• Transmitter output—If a transmitter package model is present (for example, the package model is
embedded, as in Altera devices and PCI-Express 8GT) or external (for example, using the "Custom"
package option), the output appears after the package model. If no package model is present, the
output appears at the transmitter output.
• Channel output—The second test point is at the end of channels.
• CTLE output—If you enable the receiver CTLE, the third test point is at the output of the CTLE.
• DFE output—The fourth test point is at the output of the receiver DFE.
Note: Custom test points are neglected with this test point option.
• Custom Test Point and Data Latch—JNEye plots the output at custom test points and the final data
latch point.
Probe Type
JNEye provides two type of probes:
• Ideal—With an ideal probe, the waveform, signal, or eye diagram is plotted by assuming that the link
is terminated with an ideal 50 ohms termination at the probe location.
• High-Impedance—With a high-impedance probe, the waveform, signal, or eye diagram is plotted by
emulating a high-impedance probe sensing the probe location.
Jitter Analysis Options
JNEye can perform jitter decomposition and analysis on a waveform at specified test points. The jitter
analysis feature is in the beta testing stage in the JNEye 15.0 release.
• Disable—Jitter analysis is disabled.
• Jitter Component—Using proprietary algorithms, JNEye performs a series of spectrum and
probability density function (PDF) analyses on the time-interval-error (TIE) record of the simulated
waveforms. The jitter decomposition algorithms extract various jitter components as shown in the
following figure.
UG-1146
2015.05.04
Link and Simulation Setting 2-19
Functional Description Altera Corporation
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