Document Outline

• Cover
• Special Attention and Precautions
• Chapter Door
• Contents
• List of Figures & Tables
  • List of Figures
  • List of Tables
• Chapter 1 General Specifications
  • 1.1 Overview
  • 1.2 Features
  • 1.3 Block Diagram
  • 1.4 Pin Description
    • 1.4.1 Pin Assignments
    • 1.4.2 Pin Functions
• Chapter 2 CPU
  • 2.1 Basic Specifications of CPU
  • 2.2 Block Diagram
  • 2.3 Programming Model
    • 2.3.1 CPU Registers
    • 2.3.2 Control Registers
  • 2.4 Instructions
    • 2.4.1 Addressing Modes
    • 2.4.2 Data Types
    • 2.4.3 Instruction Set
  • 2.5 Interrupts
    • 2.5.1 Overview of Interrupts
    • 2.5.2 Registers
    • 2.5.3 Interrupt Types
    • 2.5.4 Interrupt Definition
• Chapter 3 Extension Instruction Specifications
  • 3.1 Operation Extension Function
  • 3.2 Extension Instructions
    • 3.2.1 Explanation of Notations
    • 3.2.2 Extension Block Register Set
    • 3.2.3 Extension Instruction Details
    • 3.2.4 Programming Notes
• Chapter 4 Memory Modes
  • 4.1 Memory Mode Types and Selection
  • 4.2 Memory Mode Pin Processing
  • 4.3 Description of Memory Mode
    • 4.3.1 Memory Extension Mode
    • 4.3.2 Processor Mode
• Chapter 5 Operating Mode
  • 5.1 Overview
  • 5.2 Reset Mode
  • 5.3 Low Power Mode
• Chapter 6 Clock Generator
  • 6.1 Overview
  • 6.2 Features
  • 6.3 Block Diagram
  • 6.4 Description of Operation
    • 6.4.1 Input Frequency Setting
    • 6.4.2 Internal Clock Supply
• Chapter 7 Internal Memory
  • 7.1 Overview
  • 7.2 Features
  • 7.3 Internal Memory Configuration
• Chapter 8 Bus Controller (BC)
  • 8.1 Overview
  • 8.2 Features
  • 8.3 Bus Configuration
  • 8.4 Block Diagram
  • 8.5 Pin Functions
  • 8.6 Description of Registers
    • 8.6.1 Memory Block 0 Control Register
    • 8.6.2 Memory Block 1 Control Register
    • 8.6.3 Memory Block 2 Control Register
    • 8.6.4 Memory Block 3 Control Register
    • 8.6.5 DRAM control register
    • 8.6.6 Refresh count register
    • 8.6.7 Page Row Address Register
    • 8.6.8 Clock Control Register
  • 8.7 Space Partitioning
  • 8.8 Operation Clocks
  • 8.9 Mode Settings
  • 8.10 Bus Cycle
  • 8.11 Store Buffer
  • 8.12 Accessing the Internal I/O Space
  • 8.13 External Memory Space Access (Non-DRAM Spaces)
    • 8.13.1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode
    • 8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode
    • 8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode
    • 8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode
    • 8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode
    • 8.13.6 8-bit Bus in Asynchronous Mode and in Address/Data Separate Mode
    • 8.13.7 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode
    • 8.13.8 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode
    • 8.13.9 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode
    • 8.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode
    • 8.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode
    • 8.13.12 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode
  • 8.14 External Memory Space Access (DRAM Space)
    • 8.14.1 DRAM Space
    • 8.14.2 DRAM page mode
    • 8.14.3 Software Page Mode
    • 8.14.4 DRAM refresh
  • 8.15 Bus Arbitration
  • 8.16 Cautions
• Chapter 9 Interrupt Controller
  • 9.1 Overview
  • 9.2 Features
  • 9.3 System Diagram
  • 9.4 Block Diagram
  • 9.5 Description of Registers
  • 9.6 Description of Operation
• Chapter 10 8-bit Timers
  • 10.1 Overview
  • 10.2 Features
  • 10.3 Block Diagram
  • 10.4 Functions
  • 10.5 Description of Registers
  • 10.6 Description of Operation
    • 10.6.1 Interval Timers and Timer Output
    • 10.6.2 Event Counting
    • 10.6.3 Cascaded Connection
    • 10.6.4 PWM Output
• Chapter 11 16-bit Timers
  • 11.1 Overview
  • 11.2 Features
  • 11.3 Block Diagram
  • 11.4 Functions
  • 11.5 Description of Registers
  • 11.6 Description of Operation of Timer 10
    • 11.6.1 Compare Register Settings
    • 11.6.2 Capture Register Settings
    • 11.6.3 Pin Output Settings
    • 11.6.4 Starting by an External Trigger
    • 11.6.5 One-shot Operation
    • 11.6.6 Interval Timer
    • 11.6.7 Event Counting
  • 11.7 Description of Operation of Timers 11, 12, and 13
    • 11.7.1 Interval Timer and Timer Output
    • 11.7.2 Event Counting
• Chapter 12 Watchdog Timer
  • 12.1 Overview
  • 12.2 Features
  • 12.3 Block Diagram
  • 12.4 Description of Registers
  • 12.5 Description of Operation
• Chapter 13 Serial Interface
  • 13.1 Overview
  • 13.2 General-purpose serial interface
    • 13.2.1 Features
    • 13.2.2 Block Diagram of General-Purpose Serial Interface
    • 13.2.3 Description of Registers for the General-Purpose Serial Interface
    • 13.2.4 Description of Operation
  • 13.3 Clock Synchronous Serial Interface
    • 13.3.1 Features
    • 13.3.2 Block Diagram of Clock Synchronous Serial Interface
    • 13.3.3 Description of Registers for the Clock Synchronous Serial Interface
    • 13.3.4 Description of Operation
  • 13.4 Universal Asynchronous Receiver-Transceiver Serial Interface
    • 13.4.1 Features
    • 13.4.2 Block Diagram of UART Serial Interface
    • 13.4.3 Description of Registers for the UART Serial Interface
    • 13.4.4 Description of Operation
• Chapter 14 A/D Converter
  • 14.1 Overview
  • 14.2 Features
  • 14.3 Block Diagram
  • 14.4 Description of Registers
  • 14.5 Description of Operation
• Chapter 15 I/O Ports
  • 15.1 Overview
  • 15.2 Port 0
    • 15.2.1 Block Diagram
    • 15.2.2 Register Descriptions
    • 15.2.3 Pin Configurations
  • 15.3 Port 1
    • 15.3.1 Block Diagram
    • 15.3.2 Register Descriptions
    • 15.3.3 Pin Configurations
  • 15.4 Port 2
    • 15.4.1 Block Diagram
    • 15.4.2 Register Descriptions
    • 15.4.3 Pin Configurations
  • 15.5 Port 3
    • 15.5.1 Block Diagram
    • 15.5.2 Register Descriptions
    • 15.5.3 Pin Configurations
  • 15.6 Port 4
    • 15.6.1 Block Diagram
    • 15.6.2 Register Descriptions
    • 15.6.3 Pin Configurations
  • 15.7 Port 5
    • 15.7.1 Block Diagram
    • 15.7.2 Register Descriptions
    • 15.7.3 Pin Configurations
  • 15.8 Port 6
    • 15.8.1 Block Diagram
    • 15.8.2 Register Descriptions
    • 15.8.3 Pin Configurations
  • 15.9 Port 7
    • 15.9.1 Block Diagram
    • 15.9.2 Register Descriptions
    • 15.9.3 Pin Configurations
  • 15.10 Port 8
    • 15.10.1 Block Diagram
    • 15.10.2 Register Descriptions
    • 15.10.3 Pin Configurations
  • 15.11 Port 9
    • 15.11.1 Block Diagram
    • 15.11.2 Register Descriptions
    • 15.11.3 Pin Configurations
  • 15.12 Port A
    • 15.12.1 Block Diagram
    • 15.12.2 Register Descriptions
    • 15.12.3 Pin Configurations
  • 15.13 Port B
    • 15.13.1 Block Diagram
    • 15.13.2 Register Descriptions
    • 15.13.3 Pin Configurations
  • 15.14 Port C
    • 15.14.1 Block Diagram
    • 15.14.2 Register Descriptions
    • 15.14.3 Pin Configurations
  • 15.15 Treatment of Unused Pins
• Chapter 16 Internal Flash Memory
  • 16.1 Overview
  • 16.2 Features
  • 16.3 Block Diagram
  • 16.4 Flash Memory Overwrite Mode and Settings
  • 16.5 Flash Memory Mode
    • 16.5.1 Description of External Pins
    • 16.5.2 Erasure Blocks
  • 16.6 On-board Write Mode
• Chapter 17 Ordering Mask ROM
  • 17.1 Overview
  • 17.2 Procedure for Ordering ROM
• Appendix
  • Appendix A. Register Map List
  • Appendix B. Instruction Set
  • Appendix C. Memory Connection Example
  • Appendix D. Pins and Their Operating Statuses upon Reset
  • Appendix E. Package Outline
• Record of Changes
• Colophon
• Sales Offices