Lenze EVF9383 - Manual (Page 125)

Configuration
2−117
l
EDSVF9383V−EXT EN 2.0
Mains failure detection of the supply module
l A digital output of the supply module is switched to the function block MFAIL via the digital
inputs DIGIN of the 93XX controller. In the example, input X5/E4 is used. Set the following
signal links:
– C0971 = 54 (DIGIN4 to MFAIL−FAULT)
– C0871 = 1000 (remove DCTRL−TRIP−SET from terminal X5/E4)
– Select the input level (HIGH or LOW active) with C0114/4
Enter the FB MFAIL at a free position into the processing table under C0465.
C 0 9 8 9 / 1
M F A I L - F A U L T
M F A I L - R E S E T
C 0 9 7 1
C 0 9 7 2
1
0
C 0 9 8 8 / 1
C 0 9 7 0
C 0 9 8 9 / 2
C T R L
M F A I L - N O U T
M F A I L - N - S E T
C 0 9 8 3
M F A I L
E 1
E 2
E 3
E 4
E 5
1
0
C 0 1 1 4 / 1 . . . 6
D I G I N
D I G I N 1
D I G I N 2
D I G I N 3
D I G I N 4
D I G I N 5
2 8
D C T R L - X 5 / 2 8
X 5
D I G I N - C I N H
1
1
S T
D I G I N 6
C 0 4 4 3
Fig. 2−94 Example of a mains failure detection by an external monitoring system
Combination of these methods
l These methods are combined via an OR link with an internal function block. In the example,
OR5 is used. Set the following signal links:
– C0688/1 = 5005 (MCTRL−DCVOLT to CMP2−IN1)
– C0688/2 = 19540 (free code C0472/20 to CMP2−IN2)
– Set the comparator function CMP2 with C0685 = 3
– C0838/1 = 10655 (CMP2−OUT to OR5−IN1)
– C0838/2 = 54 (DIGIN5 to OR5−IN2)
– C0971 = 10570 (OR5−OUT to MFAIL−FAULT)
Enter the function blocks CMP2, OR5 and MFAIL at free positions into the processing table under
C0465.
C 0 9 8 9 / 1
M F A I L - F A U L T
M F A I L - R E S E T
C 0 9 7 1
C 0 9 7 2
1
0
C 0 9 8 8 / 1
C 0 9 7 0
C 0 9 8 9 / 2
C T R L
M F A I L - N O U T
M F A I L - N - S E T
C 0 9 8 3
M F A I L
C 0 6 8 6
C 0 6 8 7
C 0 6 8 9 / 1
C M P 2
C M P 2 - O U T C M P 2 - I N 1
C 0 6 8 9 / 2
C M P 2 - I N 2
C 0 6 8 8 / 1
C 0 6 8 8 / 2
C 0 6 8 5
C 0 4 7 2 / 2 0
M C T R L - D C V O L T
O R 5
³ 1
O R 5 - I N 1
O R 5 - I N 2
O R 5 - I N 3
O R 5 - O U T
C 0 8 3 9 / 1
C 0 8 3 9 / 2
C 0 8 3 9 / 3
C 0 8 3 8 / 1
C 0 8 3 8 / 2
C 0 8 3 8 / 3
F I X E D 0
E 1
E 2
E 3
E 4
E 5
1
0
C 0 1 1 4 / 1 . . . 6
D I G I N
D I G I N 1
D I G I N 2
D I G I N 3
D I G I N 4
D I G I N 5
2 8
D C T R L - X 5 / 2 8
X 5
D I G I N - C I N H
1
1
S T
D I G I N 6
C 0 4 4 3
Fig. 2−95 Example of a mains failure detected by different sources