Lenze EVF9383 - Manual (Page 47)

Configuration
Use of funktion blocks
2−39
l
EDSVF9383V−EXT EN 2.0
2.3.4 Entries in the processing table
The 93XX controller provides a certain computing time for FB processing. Since type and number
of the FBs used may vary in the individual applications, the controller does not continuously calculate
all FBs available. Under code C0465 you can find a processing table which contains only the FBs that
are used in the application. In this way, the drive system is ideally adapted to the application. If
additional FBs are added to an existing configuration, they must be entered into the processing table.
For the entry, the following points must be observed:
The number of FBs to be processed is limited
Every configuration can contain maximally 50 FBs. Every FB needs a certain processing time (run
time). Code C0466 indicates the remaining process time for FB processing. When the process time
is used up, you cannot add any further FBs.
Order of FB entries
In general, the entries under C0465 can be made in any order. However, with highly dynamic drive
tasks, the order of the entries may be important. Usually, we recommend to adapt the order of the
entries to the signal flow.
Example:
AND1
&
AND1-IN1
AND1-IN2
AND1-IN3
AND1-OUT
C0821/1
C0821/2
C0821/3
C0820/1
C0820/2
C0820/3
AND2
&
AND2-IN1
AND2-IN2
AND2-IN3
AND2-OUT
C0823/1
C0823/2
C0823/3
C0822/1
C0822/2
C0822/3
OR1
≥1
OR1-IN1
OR1-IN2
OR1-IN3
OR1-OUT
C0831/1
C0831/2
C0831/3
C0830/1
C0830/2
C0830/3
E1
E2
E3
E4
E5
1
0
C0114/1...5
DIGIN DIGIN1
DIGIN2
DIGIN3
DIGIN4
DIGIN5
C0443
A1
A2
A3
A4
1
0
C0118/1...4
DIGOUT
DIGOUT1
DIGOUT2
DIGOUT3
DIGOUT4
C0117/1
C0117/2
C0117/3
C0117/4
C0444/4
C0444/3
C0444/2
C0444/1
FIXED0
FIXED1
Fig. 2−19 Configuration example
Structure of the processing table for the configuration example in Fig. 2−19:
1. DIGIN need not be entered into the processing table.
2. AND1 is the first FB because it receives its input signals from DIGIN and only has successors.
3. OR1 is the second FB because its signal source is the output of AND1 (predecessor). I.e. the
output signal in AND1 must first be generated before it can be processed in OR1. OR1 also
has a successor. I.e. OR1 must be entered before its successor in the processing table.