Altera Stratix V Avalon-ST - Manual (Page 100)

Uncorrectable Error Mask Register
Table 5-42: Uncorrectable Error Mask Register - 0x148 (ARI supported) or 0x108 (ARI not supported)
Bits Register Description
Default Value
Access
[31:21] Reserved. 0 RO
[20] When set, masks an Unsupported Request Received 0
RW1C
[19] When set, masks an ECRC Error Detected 0
RW1C
[18] When set, masks a Malformed TLP Received 0
RW1C
[17] When set, masks Receiver Overflow 0
RW1C
[16] When set, masks an unexpected Completion was received
0
RW1C
[15] When set, masks a Completer Abort (CA) was transmitted
0
RW1C
[14] When set, masks a Completion Timeout
0
RW1C
[13] When set, masks a Flow Control protocol error
0
RW1C
[12] When set, masks that a poisoned TLP was received
0
RW1C
[11:5]
Reserved
0 RO
[4] When set, masks a Data Link Protocol error
0
RW1C
[3:0] Reserved 0 RO
Uncorrectable Error Severity Register
If a severity bit is 0, the core reports a Fatal error to the Root Port. If a severity bit is 1, the core reports a
Non-Fatal error to the Root Port.
Table 5-43: Uncorrectable Error Severity Register - 0x14C (ARI supported) or (0x10C ARI not supported)
Bits Register Description
Default Value
Access
[31:21] Reserved 0 RO
[20] Unsupported Request Received 0
RW
[19] ECRC Error Detected 0
RW
5-26 Uncorrectable Error Mask Register
UG-01097_sriov
2014.12.15
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