Power management – Altera Stratix V Avalon-ST User Manual
Page 33
Parameter
Value
Description
Slot power scale
0–3
Specifies the scale used for the Slot power limit. The following
coefficients are defined:
• 0 = 1.0x
• 1 = 0.1x
• 2 = 0.01x
• 3 = 0.001x
The default value prior to hardware and firmware initialization is
b’00. Writes to this register also cause the port to send the
Set_
Slot_Power_Limit
Message.
Refer to Section 6.9 of the PCI Express Base Specification Revision for
more information.
Slot power limit
0–255
In combination with the Slot power scale value, specifies the upper
limit in watts on power supplied by the slot. Refer to Section 7.8.9 of
the PCI Express Base Specification for more information.
Slot number
0-8191
Specifies the slot number.
Related Information
Power Management
Table 3-9: Power Management Parameters
Parameter
Value
Description
Endpoint L0s
acceptable
latency
Maximum of 64 ns
Maximum of 128 ns
Maximum of 256 ns
Maximum of 512 ns
Maximum of 1 us
Maximum of 2 us
Maximum of 4 us
No limit
This design parameter specifies the maximum acceptable
latency that the device can tolerate to exit the L0s state for any
links between the device and the root complex. It sets the
read-only value of the Endpoint L0s acceptable latency field of
the
Device Capabilities Register
(0x084).
This Endpoint does not support the L0s or L1 states. However,
in a switched system there may be links connected to switches
that have L0s and L1 enabled. This parameter is set to allow
system configuration software to read the acceptable latencies
for all devices in the system and the exit latencies for each link
to determine which links can enable Active State Power
Management (ASPM). This setting is disabled for Root Ports.
The default value of this parameter is 64 ns. This is the safest
setting for most designs.
UG-01097_sriov
2014.12.15
Power Management
3-13
Parameter Settings
Altera Corporation