Altera Stratix V Avalon-ST - Manual (Page 37)

Avalon-ST TX Interface
Table 4-1: 128- or 256-Bit Avalon-ST TX Datapath
Signal Direction Description
tx_st_data[<n>-1:0] Input Data for transmission. Transmit data bus. When using a 128-bit
Avalon-ST bus, the width of
tx_st_data
is 128 bits. When using
a 256-bit Avalon-ST bus, the width of
tx_st_data
is 256 bits.
The Application Layer must provide a properly formatted TLP
on the TX interface. The mapping of message TLPs is the same as
the mapping of Transaction Layer TLPs with 4 dword headers.
The number of data cycles must be correct for the length and
address fields in the header. Issuing a packet with an incorrect
number of data cycles results in the TX interface hanging and
becoming unable to accept further requests.
<n> = 128 or 256.
tx_st_sop Input Indicates first cycle of a TLP when asserted together with
tx_st_
valid
.
tx_st_eop Input Indicates last cycle of a TLP when asserted together with
tx_st_
valid
.
tx_st_ready
(3) Output Indicates that the Transaction Layer is ready to accept data for
transmission. The core deasserts this signal to throttle the data
stream.
tx_st_ready
may be asserted during reset. The Applica‐
tion Layer should wait at least 2 clock cycles after the reset is
released before issuing packets on the Avalon-ST TX interface.
The Application Layer can monitor the
reset_status
signal to
determine when the IP core has come out of reset.
If
tx_st_ready
is asserted by the Transaction Layer on cycle <n>
, then
<n + readyLatency>
is a ready cycle, during which the
Application Layer may assert
valid
and transfer data.
When
tx_st_ready
,
tx_st_valid
and
tx_st_data
are
registered (the typical case), Altera recommends a
readyLa-
tency
of 2 cycles to facilitate timing closure; however, a
readyLatency
of 1 cycle is possible. If no other delays are added
to the read-valid latency, the resulting delay corresponds to a
readyLatency
of 2.
(3) To be Avalon-ST compliant, your Application Layer must have a
readyLatency
of 1 or 2 cycles.
4-2 Avalon-ST TX Interface
UG-01097_sriov
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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