Altera Stratix V Avalon-ST - Manual (Page 42)

Signal Direction Description
rx_st_err Output Indicates that there is an uncorrectable error correction coding
(ECC) error in the internal RX buffer. Active when ECC is
enabled. ECC is automatically enabled by the Quartus II
assembler. ECC corrects single-bit errors and detects double-bit
errors on a per byte basis.
When an uncorrectable ECC error is detected,
rx_st_err
is
asserted for at least 1 cycle while
rx_st_valid
is asserted.
Altera recommends resetting the Stratix V Hard IP for PCI
Express when an uncorrectable double-bit ECC error is detected.
Related Information
Avalon Interface Specifications.
UG-01097_sriov
2014.12.15
Avalon‑ST RX Interface 4-7
Interfaces and Signal Descriptions Altera Corporation
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