Pci express and pci capabilities parameters – Altera Stratix V Avalon-ST User Manual

Page 28

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Parameter

Value

Description

MSI-X Table

BAR Indicator

[2:0]

Specifies which one of a function’s BAR number. This field is

read-only. For 32-bit BARs, the legal range is 0–5. For 64-bit

BARs, the legal range is 0, 2, or 4.

MSI-X Pending

Bit Array (PBA)

Offset

[31:0]

Points to the MSI-X Pending Bit Array table. It is offset from

the BAR value indicated in MSI-X Table BAR Indicator. The

lower 3 bits of the PBA BIR are set to zero by software to form

a 32-bit qword-aligned offset. This field is read-only.

MSI-X PBA BAR

Indicator

[2:0]

Specifies which BAR number contains the MSI-X PBA. For

32-bit BARs, the legal range is 0–5. For 64-bit BARs, the legal

range is 0, 2, or 4. This field is read-only.

Legacy Interrupts

PF0 Interrupt

Pin

inta–intd

Applicable for PFs only to support legacy interrupts. When

enabled, the core receives interrupt indications from the

Application Layer on its

INTA_IN

,

INTB_IN

,

INTC_IN

and

INTD_IN

inputs, and sends out

Assert_INTx

or

Deassert_

INTx

messages on the link in response to their activation or

deactivation, respectively.
You can configure the Physical Functions with separate

interrupt pins. Or, both functions can share a common

interrupt pin.

PF1 Interrupt

Pin

inta–intd

PF0 Interrupt

Line

0-255

Defines the input to the interrupt controller (IRQ0 - IRQ15)

in the Root Port that is activated by each

Assert_INTx

message.

PF1 Interrupt

Line

0-255

Note:
1. Throughout this user guide, the terms word, dword and qword have the same meaning that they have

in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

Related Information

PCI Express Base Specification Revision 2.1 or 3.0

PCI Express and PCI Capabilities Parameters

This group of parameters defines various capability properties of the IP core. Some of these parameters

are stored in the PCI Configuration Space - PCI Compatible Configuration Space. The byte offset

indicates the parameter address.

3-8

PCI Express and PCI Capabilities Parameters

UG-01097_sriov

2014.12.15

Altera Corporation

Parameter Settings

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