Altera Stratix V Avalon-ST - Manual (Page 34)

Parameter Value Description
Endpoint L1
acceptable
latency
Maximum of 1 us
Maximum of 2 us
Maximum of 4 us
Maximum of 8 us
Maximum of 16 us
Maximum of 32 us
No limit This value indicates the acceptable latency that an Endpoint
can withstand in the transition from the L1 to L0 state. It is an
indirect measure of the Endpoint’s internal buffering. It sets
the read-only value of the Endpoint L1 acceptable latency field
of the
Device Capabilities Register
.
This Endpoint does not support the L0s or L1 states. However,
a switched system may include links connected to switches
that have L0s and L1 enabled. This parameter is set to allow
system configuration software to read the acceptable latencies
for all devices in the system and the exit latencies for each link
to determine which links can enable Active State Power
Management (ASPM). This setting is disabled for Root Ports.
The default value of this parameter is 1 µs. This is the safest
setting for most designs.
PHY Characteristics
Table 3-10: PHY Characteristics
Parameter Value Description
Gen2 transmit
deemphasis
3.5dB
6dB
Specifies the transmit de-emphasis for Gen2. Altera
recommends the following settings:
• 3.5dB: Short PCB traces
• 6.0dB: Long PCB traces.
Use ATX PLL On/Off When enabled, the Hard IP for PCI Express uses the ATX PLL
instead of the CMU PLL Using the ATX PLL instead of the
CMU PLL reduces the number of transceiver channels that are
necessary for Gen1 and Gen2 variants. This option requires
the use of the soft reset controller and does not support the
CvP flow. For more information about channel placement,
refer to Serial Data Signals on page 4-30.
Enable Common
Clock Configura‐
tion (for lower
latency)
On/Off When you turn this option on, the Application Layer and
Transaction Layer use a common clock. Using a common
clock reduces datapath latency because synchronizers are not
necessary.
This parameter is only available for the Avalon-ST interface.
3-14 PHY Characteristics
UG-01097_sriov
2014.12.15
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