Altera Stratix V Avalon-ST - Manual (Page 18)

Figure 2-4: Steps To Perform a DMA Read
sriov_top_dma_gen3_x8_256.qsys
Hard IP for PCI Express
SR-IOV Bridge
Rd_DC0 Rd_DC1 Rd_DC2 Rd_DC3
Read DMA Router
APPs - sriov_dma_app_g3x8_256b.qsys
rddc_ctl - rddc_ctl_256b.qsys wrdc_ctl - wrdc_ctl_256b.qsys
Wr_DC0 Wr_DC1 Wr_DC2 Wr_DC3
Write DMA Router
User Application Logic (On-Chip Memories)
DMA Write TX Slave RX Master DMA Read
1
3
5
4
6
6
2, 6
The Read DMA operation includes the following steps:
1. The Descriptor Controller sends read descriptor instruction to initiate a DMA read.
2. The Descriptor Controller transmits a Memory Read TLP to the host starting at the source address.
3. The host returns DMA read data on the Avalon-ST interface.
4. The DMA Read Controller writes data to the destination address in the Application Layer memory.
5. The DMA Read module reports done status for each descriptor to the Descriptor Controller.
6. When all descriptors are complete, the Descriptor Controller sets the done bit of the last entry in the
descriptor table in host memory. The DMA Read Descriptor Controller sends this update to the TX
Slave. The TX Slave drives the update to the Hard IP for PCI Express.
UG-01097_sriov
2014.12.15
Understanding the DMA Functionality 2-7
Getting Started with the SR-IOV DMA Example Design Altera Corporation
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