Datasheet – Altera Stratix V Avalon-ST User Manual
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Datasheet
1
2014.12.15
UG-01097_sriov
Stratix V Avalon-ST Interface with SR-IOV for PCIe Datasheet
Altera
®
Stratix
®
V FPGAs include a configurable, hardened protocol stack for PCI Express
®
that is
compliant with PCI Express Base Specification 2.1 or 3.0. The Stratix V Hard IP for PCI Express with
Single Root I/O Virtualization (SR-IOV) IP core consists of this hardened protocol stack and the SR-IOV
soft logic. The SR-IOV soft logic uses Configuration Space Bypass mode to bypass the hardened Configu‐
ration Space. It implements the following functions in soft logic:
• Configuration Spaces for up to 2 PCIe Physical Functions (PFs) and a maximum of 128 Virtual
Functions (VFs) for both PFs
• BAR checking logic
• Support for the following interrupt types:
• MSI for PFs
• MSI-X for PFs and VFs
• Legacy interrupts for PFs
• Support for Advanced Error Reporting (AER) for PFs
• Support for Function Level Reset (FLR) for PFs and VFs
• Support for x2, x4, and x8 links using a 128- or 256-bit Avalon-ST datapath
For details of the Configuration Space Bypass mode interface refer to the Configuration Space Bypass
Mode Interface Signals in the Stratix V Hard IP for PCI Express User Guide for the Avalon Streaming
Interface
Figure 1-1: Stratix V PCIe Variant with SR-IOV
The following figure shows the high-level modules and connecting interfaces for this variant.
Application
Layer
(User Logic)
Avalon-ST
Interface
PCIe Hard IP
with SR-IOV
Block
PIPE
Interface
PHY IP Core
for PCIe
(PCS/PMA)
Serial Data
Transmission
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