Altera Stratix V Avalon-ST - Manual (Page 20)

These files specify Synopsys Design Constraints, Quartus II design constraints, and top-level
connectivity.
3. On the Quartus II file menu, select the New Project Wizard.
a. Specify top_hw for the project name.
b. To specify design constraints, on the Tools menu, select Tcl Scripts.
The Tcl Script dialog box appears.
c. Scroll down to select top.tcl. Click run.
The Quartus II software runs the design constraints.
4. On the Processing menu, select Start compilation.
Quartus II compilation begins.
Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as
a Separate Component
You can also instantiate the Stratix V Hard IP for PCI Express IP Core as a separate component for
integration into your project.
You can use the Quartus II IP Catalog and IP Parameter Editor to select, customize, and generate files
representing your custom IP variation. The IP Catalog (Tools > IP Catalog) automatically displays IP
cores available for your target device. Double-click any IP core name to launch the parameter editor and
generate files representing your IP variation.
For more information about the customizing and generating IP Cores refer to Specifying IP Core
Parameters and Options in Introduction to Altera IP Cores. For more information about upgrading older
IP cores to the current release, refer to Upgrading Outdated IP Cores in Introduction to Altera IP Cores.
Note: Your design must include the Transceiver Reconfiguration Controller IP Core and the Altera PCIe
Reconfig Driver. Refer to the figure in the Qsys Design Flow section to learn how to connect this
components.
Related Information
• Introduction to Altera IP Cores
• Managing Quartus II Projects
UG-01097_sriov
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Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate
Component
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Getting Started with the SR-IOV DMA Example Design Altera Corporation
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