Altera Stratix V Avalon-ST User Manual
Page 14
Qsys Subsystem
Description
wrdc_ctl_256b.qsys
This subsystem implements the Write Descriptor Controller for 4 Write
DMA channels.
Note: File names that include 256b have a 256-bit interface to the Application Layer. File names that
include 128b have a 128-bit interface to the Application Layer.
2. Rename the top-level Qsys file, sriov_top_dma_gen3_x8_256b.qsys, to top.qsys.
3. In your working directory, start Qsys, by typing the following command:
qsys-edit
4. Open top.qsys.
The following figure shows the Qsys system.
Figure 2-2: Top-Level Qsys System for SR-IOV Gen3 x8 DMA Example Design
5. On the Generate menu, select Generate Testbench System.
The Generation dialog box appears.
UG-01097_sriov
2014.12.15
Generating the Example Design Testbench
2-3
Getting Started with the SR-IOV DMA Example Design
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