Sdc timing constraints – Altera Stratix V Avalon-ST User Manual
Page 138
Related Information
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
SDC Timing Constraints
Note: You may need to change the name of the Reconfiguration Controller clock,
reconfig_xcvr_clk
,
to match the clock name used in your design. The following error message indicates that
TimeQuest could not match the constraint to any clock in your design:
Ignored filter at altpcied_sv.sdc(25): *reconfig_xcvr_clk* could not be matched
with a port or pin or register or keeper or net
Example 10-1: SDC Timing Constraints Required for the Stratix V Hard IP for PCIe and Design
Example
# Constraints required for the Hard IP for PCI Express
# derive_pll_clock is used to calculate all clock derived from
# PCIe refclk. It must be applied once across all of the SDC
# files used in a project
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
#########################################################################
# Reconfig Controller IP core constraints
# Set reconfig_xcvr clock:
# this line will likely need to be modified to match the actual
# clock pin name used for this clock, and also changed to have
# the correct period set for the clock actually used
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}
{*reconfig_xcvr_clk*}
######################################################################
# Hard IP testin pins SDC constraints
set_false_path -from [get_pins -compatibility_mode *hip_ctrl*]
######################################################################
# These additional constraints are for Gen3 only
set_false_path -from [get_clocks {reconfig_xcvr_clk}] -to [get_clocks
{*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}]
set_false_path -from [get_clocks {*|altpcie_hip_256_pipen1b|
stratixv_hssi_gen3_pcie_hip|coreclkout}] -to
[get_clocks {reconfig_xcvr_clk}]
Additional
.sdc
timing are in the
/<project_dir>/synthesis/submodules
directory.
UG-01097_sriov
2014.12.15
SDC Timing Constraints
10-3
Design Implementation
Altera Corporation