Correctable error mask register, Virtual function registers – Altera Stratix V Avalon-ST User Manual
Page 102
Bits
Register Description
Default Value
Access
[0]
When set, indicates a Receiver Error
0
RW1C
Related Information
Correctable Error Mask Register
Table 5-45: Correctable Error Mask Register - 0x154 (ARI supported) or (0x114 ARI not supported)
Bits
Register Description
Default Value
Access
[31:14]
Reserved
0
RO
[13]
When set, masks an Advisory Non-Fatal Error
0
RW1C
[12]
When set, masks a Replay Timeout
0
RW1C
[11:9]
Reserved
0
RO
[8]
When set, masks a Replay Number Rollover
0
RW1C
[7]
When set, masks a Bad DLLP received
0
RW1C
[6]
When set, masks a Bad TLP received
0
RW1C
[5:1]
Reserved
0
RO
[0]
When set, masks a Receiver Error
0
RW1C
Related Information
Virtual Function Registers
The SR-IOV Bridge implements the PCI and PCI Express Configuration Spaces for a maximum of 128
Virtual Functions. The VF registers available are a subset of the PF registers. For example, the VFs do not
implement the Link Capabilities 2 register. The definitions of VF registers are the same as PF registers.
For additional details, refer to the PCI Express Base Specification 3.0.
5-28
Correctable Error Mask Register
UG-01097_sriov
2014.12.15
Altera Corporation
Registers